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Obsolescence Notice
This product is obsolete. This information is available for your convenience only. For more information on Zarlink's obsolete products and replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
PRELIMINARY
INFORMATION
Distinctive Characteristics
8 10Mbps Ethernet Access Ports Direct interface with 10BaseT transceiver 0.5 micron 3.3 Volt CMOS process 352-BGA package Operating frequency -33 -40 -50 -66 mum 33 MHz maximum 40 MHz maximum 50 MHz maximum 66.66 MHz maxi-
EA218E - 8-Port Ethernet Access Controller
XpressFlow 2020 Ethernet Routing Switch Chipset
XPRESSFLOW BUS
MANAGEMENT BUS 16 32
32
LOCAL BUFFER MEMORY
EA-218E 8-Port Ethernet Access Controller
Port Port Port Port Port Port Port Port 0 1 2 3 4 5 6 7
32-bit Local Buffer Memory Interface Supports 128k to 1M bytes Utilize high performance 32-bit Synchronous Burst SRAM Hardware assisted Buffer and Queue Management 16-bit Management Bus I/O Interface Allows host to access Control Registers & Local Buffer Memory Big and Little Endian CPUs Direct interface to standard microprocessors, including 386, 486 families and Motorola MPC series embedded processors 32-bit XpressFlow Bus Interface Uses Granule for frame transferring between Access Controllers Unicast, multicast, and broadcast frames Also detects IEEE 802.3X MAC Control frames Works together with SC-220 XpressFlow Engine Forwards frames at full line-rate Distributed Flow CachingTM to reduce frame forwarding latency Half and Full Duplex operation Programmable Flow Control Jam Collision for Half Duplex Mode Transmit Flow Control Frame for IEEE 802.3x Full Duplex Mode Supports Store-&-Forward frame forward(c) 1998 Zarlink Semiconductor, Inc. 1 Rev.2.1 - February, 1999
8 10BaseT Ports
10BaseT Phyiscal Layer Transceiver
Block DiagramEA218E 8-Port Ethernet Access Controller General Description The EA-218E provides eight 10Mbps Ethernet network access interface ports. The EA-218E provides the Ethernet MAC protocols, handles the local buffer memory interface and management, arbitrates among multiple priority queues, and interfaces with the XpressFlow Engine and other Access Controllers through the XpressFlow message passing protocol.
Related Components:
SC220 - XpressFlow Engine EA218 - 6-port 10 + 2-port 10/100 Ethernet Access Controller EA234 - 4-port 10/100Mbps Ethernet Access Controller
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XpressFlow-2020 Series - Ethernet Switch Chipset
ing mode
EA218E 8-Port 10Mb Ethernet Access Controller
XPRESSFLOW BUS
Characteristics Continue
Automatically selects the optimized mode for forwarding Allows manual frame forwarding mode selection override Multi-Media ready with QoS supports Four frame transmission priority queues Complies with IEEE 802.1 Bridge Standard Assigns one unique MAC Address for each port VLAN ID Tagging & Stripping Auto padding if necessary after stripping Automatic retry frame transmission Transmit collision Transmit buffer under-run Automatic receive filtering for bad frames for Store & Forward Mode Bad FCS Short events or frames under 64 bytes Long events or frames over 1518/1522 bytes Automatic statistic collection for RMON
Address Mapping Table
32
MANAGEMENT BUS
32 16
EA-218E
Local Buffer Memory Local Buffer Memory Interface
XpressFlow Bus Interafce
Management Bus Interafce
32
Automatic Buffer Manager
MAC Interface
32
MAC Port #0 to #7
Port 0 1 2 3 4 5 6 7
8-Port 10BaseT PHY
Port 0
1
2
3
4
5
6
7
Block Diagram - EA218E 8-Port Ethernet Access Controller
Typical Application: A 16-port Ethernet Switch with 4-Fast Ethernet
RS232 Local Control Console
Buffer RAM
SC220 XpressFlow Engine
Flash ROM
Switch Manager CPU
DRAM
Management Bus XpressFlow Bus
Buffer RAM
EA218E 8-Port Ethernet Access Controller
Buffer RAM
EA218E 8-Port Ethernet Access Controller
Buffer RAM
EA234 4-Port Ethernet Access Controller
8 Ethernet ports
8 Ethernet ports
Four 100M Fast Ethernet ports
System Block Diagram -16-Port Ethernet Switch with 4 Fast Ethernet Up-Links
(c) 1998 Zarlink Semiconductor, Inc.
2
Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
1. PIN ASSIGNMENT
1.1 Logic Symbol EA-218E
L_A[18:2] L_BWE[3:0]# L_WE[3:0]# L_OE[3:0]# L_ADSC# L_CLK P_D[15:0] P_A[11:1] P_CS# P_ADS# P_RWC P_BS16# P_RDY# P_INT P_RST# P_CLK S_D[31:0] S_MSGEN# S_EOF# S_IRDY S_TABT# S_OVLD# S_HPREQ# S_REQ# S_GNT# S_CLK
4 4 4
Control Buffer Memory Interface
L_D[31:0]
Test Pin
T_MODE Tm_RXD Tm_RXC Tm_TXC Tm_TXEN Tm_TXD Tm_LPBK Tm_FD Tm_COL Tm_CRS Tm_LNK
(c) 1998 Zarlink Semiconductor, Inc.
XpressFlow Bus Interface
Management Bus Interface
Port [7:0] 10M Serial Interface 3
Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset 1.2 Pin Assignment (Preliminary)
Note: # Input In-ST Output Out-OD I/O-TS I/O-OD 5VT
EA218E 8-Port 10Mb Ethernet Access Controller
Active low signal Input signal Input signal with Schmitt-Trigger Output signal (Tri-State driver) Output signal with Open-Drain driver Input & Output signal with Tri-State driver Input & Output signal with Open-Drain driver Input with 5V Tolerance Output signal with programmable polarity. Input or output pins with weak internal pull up resistors (50k to 100k Ohms each) These pins are reserved for internal use only. They should be left unconnected. Max IOL / IOH Name and Functions 16mA Management Bus - Data Bit [15:0]
Pin No(s). Management Bus Interface J25,K26,L24,K25,L26, M24,L25,M26,N24,M25, P24,N26,N25,R24,P26, P25 C26,D24,C25,E24,D26, D25,F24,E26,E25,G24, F26 F25 H25 J24 G25 G26 H26 J26 K24 XpressFlow Bus Interface C23,A23,B22,C22,A22 B21,D20,C21,A21,B20, A20,C20,B19,A19,C19, B18,A18,B17,C18,A17, D17,B16,C17,A16,B15, A15,C16,B14,D15,A14, C15,B13 B12 A12 C14 C13 B23 A24 B24 A13 D13
Symbol
Type
P_D[15:0]
TTL I/O-TS (5VT)
P_A[11:1] P_ADS# P_RWC P_RDY# P_BS16# P_CS# P_INT P_RST# P_CLK S_D[31:27] / P_C[0:4] S_D[26:0]
TTL In (5VT) TTL In (5VT) TTL In (5VT) TTL Out-OD TTL Out-OD TTL In (5VT) CMOS Output TTL In-ST (5VT) TTL In (5VT) CMOS I/O-TS CMOS I/O-TS
Management Bus - Address Bit [11:1] Management Bus - Address Strobe Management Bus - Read/Write Control Management Bus - Data Ready Management Bus - 16 bit Data Bus Management Bus - Chip Select Management Bus - Interrupt Request Management Bus - Master Reset Management Bus - Bus Clock XpressFlow Bus - Data Bit [31:27] or Management Bus Interface Configuration bit [0:4] XpressFlow Bus - Data Bit [26:0]
16mA 16mA 4mA
12 mA 12mA
S_MSGEN# S_EOF# S_IRDY S_TABT# S_HPREQ# S_REQ# S_GNT# S_OVLD# S_CLK
CMOS I/O-TS CMOS I/O-TS CMOS I/O-TS CMOS I/O-OD CMOS I/O-OD CMOS Output CMOS Input CMOS Input CMOS Input
12 mA 12mA 12 mA 12 mA 12mA 4mA
XpressFlow Bus - Message Envelope XpressFlow Bus - End of Frame XpressFlow Bus - Initiator Ready XpressFlow Bus - Target Abort XpressFlow Bus - High Priority Request XpressFlow Bus - Bus Request to SC201 XpressFlow Bus - Bus Grant from SC201 XpressFlow Bus - Bus Overload XpressFlow Bus - Clock
(c) 1998 Zarlink Semiconductor, Inc.
4
Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset
Pin No(s). Symbol TTL I/O-TS
EA218E 8-Port 10Mb Ethernet Access Controller
Type 8mA Name and Functions Local Memory Bus - Data Bit [31:0]
Control Buffer Memory Interface L_D[31:0] M4,N2,L3,M1,M2,L1,K3, L2,K4,K1,J3,K2,J1,J2, H3,H1,H2,G3,G1,G2,F1,F3,F 2,E1,E3,E2,D1,D3,D2,C1,C2, B1 A6,B6,C8,A7,D8,D7,C9, L_A[18:2] A8,B8,A9,C10,B9,D10, A10,C11,B10,A11 C7 L_A[19] / L_OE[3]# D5,A5,A3 L_OE[2:0]# D7,E4,B5,C4 L_WE[3:0]# C6,B4,A4,C5 L_BWE[3:0]# B3 L_ADSC# G4 L_CLK Ethernet Access Port cont. [7:0] AF20,AE17,AD12,AD9, T[7:2]_RXD AC2,T25 AC25,AF6 T[1:0]_RXD AD19,AD16,AE14,AF10,AC2 T[7:2]_RXC 1U24 AC24,AE7 T[1:0]_RXC AF18,AD14,AE12,AF8, T[7:0]_TXC W2,AA25,AE22,AD1 AE19,AF15,AF12,AD8, T[7:2]_TXEN W1,AA24 AF22,AF2 T[1:0]_TXEN AE20,AF16,AF13,AE10, T[7:2]_TXD Y1,W25 AF23,AE4 T[1:0]_TXD AD18,AD15,AE13,AF9, T[7:2]_LPBK Y2,Y26 AE23,AF3 T[1:0]_LPBK AF19,AE16,AD11,AE9, T[7:2]_FD V3,AA26 AD21,AE3 T[1:0]_FD AD17,AE15,AF11,AE8, T[7:2]_COL V1,AB26 AD20,AC23 T[1:0]_COL AE18,AD13,AD10,AD7, T[7:2]_CRS U3,AB24, AF21,AD2 T[1:0]_CRS AF17,AF14,AE11,AF7, T[7:2]_LNK V2,AB25, AE21,AB3 T[1:0]_LNK
CMOS Output
8mA
Local Memory Bus - Address Bit [17:2]
CMOS Output CMOS Output CMOS Output CMOS Output CMOS Output CMOS Output TTL In (5VT) TTL In (5VT) TTL In (5VT) TTL In (5VT) TTL In (5VT) CMOS Out CMOS Output CMOS Out CMOS Output CMOS Out CMOS Output CMOS Out CMOS Output TTL In (5VT) TTL In (5VT) TTL In (5VT) TTL In (5VT) TTL In (5VT) TTL In (5VT)
8mA 2mA 2mA 8mA 8mA 8mA
Local Memory Bus - Address Bit [19] or Memory Read Chip Select [3] Local Memory Read Chip Select [2:0] Local Memory Write Chip Select [3:0] Local Memory Byte Write Enable, Byte [3:0] Local Memory Controller Address Status Local Memory Clock input Receive Data - (one for each 10Mbps Serial Interface Port) Receive Clock - (one for each 10Mbps Serial Interface Port) Transmit Clock - (one for each 10Mbps Serial Interface Port) Transmit Enable - (one for each 10Mbps Serial Interface Port) Transmit Data - (one for each 10Mbps Serial Interface Port) Loop Back Enable - (one for each 10Mbps Serial Interface Port) Full Duplex Mode - (one for each 10Mbps Serial Interface Port) Collision Detected - (one for each 10Mbps Serial Interface Port) Carrier Sense - (one for each 10Mbps Serial Interface Port) Link Status - (one for each 10Mbps Serial Interface Port)
4mA
4mA
2mA
2mA
(c) 1998 Zarlink Semiconductor, Inc.
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Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
Symbol Type Max IOL / IOH Name & Functions 2mA 4mA Test Pin - Set Test Mode upon Reset, and provides test status output during test mode Test Pins - Reserved for internal use only
Pin No(s). Test Facility A25
T_MODE
CMOS I/O-TS CMOS Output
N1,M3,P2,P1,N3,R2,P3,R1,T T_D[15:10] 2R3,T1,R4,U2,T3,U1,U4 Pin No(s). Power Pins D6,D11,D16,D21,F4, VDD F23,L4,L23,T4,T23,AA4,AA23 AC6,AC11,AC16,AC21 VSS A1,A2,A26,B2,B25,B26, C3,C24,D4,D9,D14,D19,D23, H4,J23,N4,P23,V4,W23,AC4, AC8,AC13, AC18,AC23,AD3,AD24, AE1,AE2,AE25,AF1, AF25 Symbol
Type Power
Name & Functions +3.3 Volt DC Supply
Power
Ground
(c) 1998 Zarlink Semiconductor, Inc.
6
Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset
1.3 Pin Reference Table: (352 pin BGA)
Pin # F26 G24 E25 E26 F24 D25 D26 E24 C25 D24 C26 F25 G26 H25 G25 J24 J26 H26 K24 P25 P26 R24 N25 N26 P24 M25 N24 M26 L25 M24 L26 K25 L24 K26 J25 D13 A13 B23 A24 B24 B12 A12 C14 C13 B13 C15 A14 D15 B14 C16 A15 B15 A16 C17 B16 D17 A17 Signal Name P_A[1] P_A[2] P_A[3] P_A[4] P_A[5] P_A[6] P_A[7] P_A[8] P_A[9] P_A[10] P_A[11] P_ADS# P_CS# P_RWC P_BS16# P_RDY# P_RST# P_INT P_CLK P_D[0] P_D[1] P_D[2] P_D[3] P_D[4] P_D[5] P_D[6] P_D[7] P_D[8] P_D[9] P_D[10] P_D[11] P_D[12] P_D[13] P_D[14] P_D[15] S_CLK S_OVLD# S_HPREQ# S_REQ# S_GNT# S_MSGEN# S_EOF# S_IRDY S_TABT# S_D[0] S_D[1] S_D[2] S_D[3] S_D[4] S_D[5] S_D[6] S_D[7] S_D[8] S_D[9] S_D[10] S_D[11] S_D[12] Pin # C18 B17 A18 B18 C19 A19 B19 C20 A20 B20 A21 C21 D20 B21 A22 C22 B22 A23 C23 A11 B10 C11 A10 D10 B9 C10 A9 B8 A8 C9 B7 D8 A7 C8 B6 A6 C7 D5 A5 A3 D7 E4 B5 C4 C6 B4 A4 C5 B3 G4 B1 C2 C1 D2 D3 D1 E2 Signal Name S_D[13] S_D[14] S_D[15] S_D[16] S_D[17] S_D[18] S_D[19] S_D[20] S_D[21] S_D[22] S_D[23] S_D[24] S_D[25] S_D[26] S_D[27] / P_C[4] S_D[28] / P_C[3] S_D[29] / P_C[2] S_D[30] / P_C[1] S_D[31] / P_C[0] L_A[2] L_A[3] L_A[4] L_A[5] L_A[6] L_A[7] L_A[8] L_A[9] L_A[10] L_A[11] L_A[12] L_A[13] L_A[14] L_A[15] L_A[16] L_A[17] L_A[18] L_A[19] / OE[3]# L_OE[2]# L_OE[1]# L_OE[0] L_WE[3]# L_WE[2]# L_WE[1]# L_WE[0]# L_BWE[3]# L_BWE[2]# L_BWE[1]# L_BWE[0]# L_ADSC# L_CLK L_D[0] L_D[1] L_D[2] L_D[3] L_D[4] L_D[5] L_D[6] Pin # E3 E1 F2 F3 F1 G2 G1 G3 H2 H1 H3 J2 J1 K2 J3 K1 K4 L2 K3 L1 M2 M1 L3 N2 M4
EA218E 8-Port 10Mb Ethernet Access Controller
Signal Name L_D[7] L_D[8] L_D[9] L_D[10] L_D[11] L_D[12] L_D[13] L_D[14] L_D[15] L_D[16] L_D[17] L_D[18] L_D[19] L_D[20] L_D[21] L_D[22] L_D[23] L_D[24] L_D[25] L_D[26] L_D[27] L_D[28] L_D[29] L_D[30] L_D[31]
AB3 T0_LNK AD2 T0_CRS AC3 T0_COL AE3 T0_FD AF3 T0_LPBK AE4 T0_TXD AF2 T0_TXEN AD1 T0_TXC AE7 T0_RXC AF6 T0_RXD AE21 T1_LNK AF21 T1_CRS AD20 T1_COL AD21 T1_FD AE23 T1_LPBK AF23 T1_TXD AF22 T1_TXEN AE22 T1_TXC AC24 T1_RXC AC25 T1_RXD AB25 T2_LNK AB24 T2_CRS AB26 T2_COL AA26 T2_FD Y26 T2_LPBK W25 T2_TXD AA24 T2_TXEN AA25 T2_TXC U24 T2_RXC T25 T2_RXD V2 T3_LNK U3 T3_CRS
Pin # V1 V3 Y2 Y1 W1 W2 AC1 AC2 AF7 AD7 AE8 AE9 AF9 AE10 AD8 AF8 AF10 AD9 AE11 AD10 AF11 AD11 AE13 AF13 AF12 AE12 AE14 AD12 AF14 AD13 AE15 AE16 AD15 AF16 AF15 AD14 AD16 AE17 AF17 AE18 AD17 AF19 AD18 AE20 AE19 AF18 AD19 AF20 A25 U4 U1 T3 U2 R4 T1 R3
Signal Name T3_COL T3_FD T3_LPBK T3_TXD T3_TXEN T3_TXC T3_RXC T3_RXD T4_LNK T4_CRS T4_COL T4_FD T4_LPBK T4_TXD T4_TXEN T4_TXC T4_RXC T4_RXD T5_LNK T5_CRS T5_COL T5_FD T5_LPBK T5_TXD T5_TXEN T5_TXC T5_RXC T5_RXD T6_LNK T6_CRS T6_COL T6_FD T6_LPBK T6_TXD T6_TXEN T6_TXC T6_RXC T6_RXD T7_LNK T7_CRS T7_COL T7_FD T7_LPBK T7_TXD T7_TXEN T7_TXC T7_RXC T7_RXD T_MODE T_D[0] T_D[1] T_D[2] T_D[3] T_D[4] T_D[5] T_D[6]
Pin # T2 R1 P3 R2 N3 P1 P2 M3 N1 D6 D11 D16 D21 F4 F23 L4 L23 T4 T23 AA4 AA23 AC6 AC11 AC16 AC21 A1 A2 A26 B2 B25 B26 C3 C24 D4 D9 D14 D19 D23 H4 J23 N4 P23 V4 W23 AC4 AC8 AC13 AC18 AC23 AD3 AD24 AE1 AE2 AE25 AF1 AF25
Signal Name T_D[7] T_D[8] T_D[9] T_D[10] T_D[11] T_D[12] T_D[13] T_D[14] T_D[15] VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Note:
Output signals with programmable polarity. Input or output pins with weak internal pull up resistors (50k to 100k Ohms each) These pins are reserved for internal use only. They should be left unconnected.
(c) 1998 Zarlink Semiconductor, Inc.
7
Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
2. FUNCTIONAL DESCRIPTION
2.1 Local Memory (Local Buffer Memory) Interface
Uses industry standard Synchronous Burst Mode SRAM up to 1M bytes 32k x 32, 64k x 32, 128k x 32, or 256k x 32 Provides separate Read and Write Chip Selects ( L_OE[3:0]# and L_WE[3:0]# ) for each memory chip Supports back to back Read or Write operations across memory chips
2.1.1 Pin Description
Symbol L_D[31:0] L_A[18:2] L_A[19] / L_OE[3]# L_OE[2:0]# L_WE[3:0]# L_BWE[3:0]# L_ADSC# L_CLK L_D[31:0] L_A[18:2] L_A[19] / L_WE[3]# L_WE[2:0]# L_OE[3:0]# L_BWE[3:0]# L_ADSC# L_CLK Note: Type TTL I/O-TS CMOS Output CMOS Output Name and Functions Local Memory Data Bus Bit [31:0] - a 32-bit synchronous data bus. Local Memory Address Bus Bit [18:2] - Bit [18:2] of a synchronous address bus. The memory address is sampled when L_CS# is enabled and L_ADSC# is asserted. Local Memory Address Bus Bit [19] or Local Memory Read Chip Select [3] - Depends on memory configuration, this pin can be used as the Local Memory Address Bit [19] or as the Local Memory Read Chip Select [3]. Local Memory Read Chip Select [2:0] - allows up to read one of the 4 banks of memory. Local Memory Write Chip Select [3:0] - allows up to write one of the 4 banks of memory. Local Memory Byte Write Enable [3:0] - use to write individual bytes. Local Memory Controller Address Status - to load a new address. Local Memory Clock - a synchronous clock to memory devices. Local Memory Data Bus Bit [31:0] - a 32-bit synchronous data bus. Local Memory Address Bus Bit [18:2] - Bit [17:2] of a synchronous address bus. The memory address is sampled when L_CS# is enabled and L_ADSC# is asserted. Local Memory Address Bus Bit [19] or Local Memory Write Chip Select [3] - Depends on memory configuration, this pin can be used as the Local Memory Address Bit [19] or as the Local Memory Write Chip Select [3]. Local Memory Write Chip Select [2:0] - allows up to write one of the 4 banks of memory. Local Memory Read Chip Select [3:0] - allows up to read one of the 4 banks of memory. Local Memory Byte Write Enable [3:0] - use to write individual bytes. Local Memory Controller Address Status - to load a new address. Local Memory Clock - a synchronous clock to memory devices.
CMOS Output CMOS Output CMOS Output CMOS Output CMOS Output TTL I/O-TS CMOS Output CMOS Output
CMOS Output CMOS Output CMOS Output CMOS Output CMOS Output
These pins have weak internal pull up resistors (50k to 100k Ohms each).
(c) 1998 Zarlink Semiconductor, Inc.
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Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.1.2 Supported Memory Configurations
EA218E 8-Port 10Mb Ethernet Access Controller
Read/Write Chip Select and High Address Bits Chip #3 Chip #2 Chip #1 Chip #0 L_A[19] / RAM Chip # of RAM Total Buffer L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# Size Chips Memory Size 32k x 32 1 2 4 64k x 32 1 2 4 128k x32 1 2 256k x32 1 128k bytes 256k bytes 512k bytes 256k bytes 512k bytes 1M bytes 512k bytes 1M bytes 1M bytes ------------------------------L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# ------------------------------L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# ---------------L_A[19] ------------------------L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]# ------L_WE[0]# L_OE[0]#
2.1.3 Bus Cycle Waveforms
L_CLK L_ADSC# L_CS# L_A[19:2] L_WE[3:0]# L_BWE[3:0]# L_OE[3:0]#
A1
A2
A3
A3+1
A3+2
A3+3
A4
A4+1
A4+2
A4+3
A5
A6
L_D[31:0] (Wr)
D1
D3
D3+1
D3+2
D3+3
D6
L_D[31:0] (Rd)
D2
D4
D4+1
D4+2
D4+3
D5
Typical Local Memory Access Operations
(c) 1998 Zarlink Semiconductor, Inc.
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Rev.2.1 - February, 1999
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.2 Processor Bus Interface
Supports various industry standard micro-processors including: Intel 186, 386, and 486 family or equivalent Motorola MPC series embedded processors Easily adapts to other industry standard CPUs Provides separate Address and Data bus Supports Big & Little Endian byte ordering
EA218E 8-Port 10Mb Ethernet Access Controller
Supports 16-bit Data Bus Supports early RDY cycle Meets timing requirement for Intel/AMD 186 family processors Supports 1X or 2X CPU Clock 2X CPU Clock for 386 family processors Provides a single interrupt signal to Switch Manager CPU
2.2.1 Pin Description
Symbol P_C[4:0] Type CMOS Input Name and Functions Processor Configuration bit [4:0]: - During the Reset Cycle, the P_C[4:0] pins provides the processor configuration. By using external weak pull-up or -down resistors, they define the External Management Bus Interface Configuration. These inputs are sampled at the trailing edge of the Reset cycle. C[0] - Defines the CPU Clock input is 1X or 2X clock C[1] - Selects either Big or Little Endian byte ordering C[2] - Defines the polarity of the P_RWC (Rd/Wr Control) input C[3] - Defines the CPU Bus width - For EA-208, it is default to 16-bit CPU Bus interface, and the setting of this bit is ignored. C[4] - Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High, the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4] is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are valid. C[0] CPU Clock Lo Hi P_A[11:1] P_D[15:0] P_ADS# P_RWC 1X Clock 2x Clock C[1] Byte Order Little Endian Big Endian C[2] RWC P_R/W# P_W/R# C[3] Bus Size n/a n/a C[4] RDY Timing Normal Early
P_RDY# P_BS16# P_CS# P_INT P_RST# P_CLK
After RESET, these pins are used as XpressFlow Bus Data bit [31:27]. TTL In (5VT) Address Bus Bit [11:1] - I/O port address TTL I/O-TS (5VT) Data Bus Bit [15:0] - a 16-bit synchronous data bus. TTL In (5VT) Address Strobe - indicates valid address is on the bus TTL Input (5VT) Read/Write Control - indicates the current bus cycle is a read or write cycle. C[1] defines the polarity of this signal during the Reset cycle. C[1]=Low P_R/W# is used for PowerPC or other similar processors. C[1]=High P_W/R# is used for 386, 486 or other similar processors TTL Out-OD Data Ready - timing indicates for bus data valid TTL Out-OD Bus Size 16 - response to bus master that the EA208 only supports 16-bit data bus width. TTL Input (5VT) Chip Select - indicates the XpressFlow Engine is the target for the current bus operation. CMOS Output Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable via chip configuration register. TTL In-ST (5VT) CPU Reset - Synchronous reset Input from Switch Manager CPU TTL In (5VT) CPU Clock - 2X Clock for 386 family, and 1X Clock for the others
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.2.2 Motorola MPC801 Processor Interface
P_CLK {CLKOUT} P_ADS# {TS#} P_A[11:1] {A[20:30]} P_CS# P_RWC {RD/WR#} P_RDY# {TA#} P_D[15:0] {D[0:15]} (in) P_D[15:0] {D[0:15]} (out)
EA218E 8-Port 10Mb Ethernet Access Controller
Note: Mnemonics with in {} are the equivalent signals defined by MPC801
Typical Motorola MPC801 CPU I/O Access Operations 2.2.3 Intel 486 Processor Interface
P_CLK P_ADS# P_A[11:1] P_CS# P_W/R# P_RDY# P_D[15:0] (in)
P_D[15:0] (out)
Typical 486 CPU I/O Access Operations
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.2.4 Intel 386 Processor Interface
P_CLK
EA218E 8-Port 10Mb Ethernet Access Controller
PH2 (internal)
PH2
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D15:0] (out)
Typical 386 CPU I/O Access Operations
P_CLK
PH2 (internal) PH2 or PH1 P_RST#
PH2
PH1
PH2
Internal PH2 Clock Synchronization **
Note: ** See Intel 386 Processor Data Book for more details
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.2.5 Register Map
Note: All 32-bit registers are D-word aligned.
EA218E 8-Port 10Mb Ethernet Access Controller
All 16-bit registers are also D-word aligned and right justified. For the Little Endian CPUs, register offset bit [1,0] are always set to be 00. For the Big Endian CPUs, register offset bit [1,0] are always set to be 10. This is a Global Register. CPU is allowed to write the Global Register of all devices by a single operation. These registers are reserved for system diagnostic usage only. I/O Offset Little Big Endian Endian hF00 hF00 hF10 hF20 hF30 hF40 hF70 hF80 hF90 hFA0 hFB0 hE08 hE18 hE28 hE40 hE50 hE68 hE6C hE68 hE6C hD00 hD30 hD90 hDA0 hDB0 hF02 hF02 hF12 hF22 hF32 hF42 hF72 hF82 hF92 hFA2 hFB2 hE08 hE18 hE28 hE42 hE52 hE68 hE6C hE68 hE6C hD02 hD32 hD92 hDA2 hDB2
Register
Description
Reg. Size 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit 32-bit 32-bit 16-bit 16-bit 32-bit 32-bit 32-bit 32-bit 16-bit 16-bit 16-bit 16-bit 16-bit
W/R
Note:
Device Configuration Registers (DCR) GCR Global Control Register DCR0 DCR1 DCR2 DCR3 DCR4 DTSR Device Status Register Signature & Revision Register ID Register Device Configuration Register Interfaces Status Register Test Register
W/---/R --/R W/R W/R --/R W/R --/R --/R W/R W/-W/R W/R W/R W/R W/R W/-W/---/R --/R W/R --/R W/R W/R --/R
Interrupt Controls ISR Interrupt Status Register - Unmasked ISRM Interrupt Status Register - Masked IMSK Interrupt Mask Register IAR Interrupt Acknowledgment Register Buffer Memory Interface MWAR Memory Write Address Reg. - Single Cycle MRAR Memory Read Address Reg. - Single Cycle MBAR Memory Address Register - Burst Mode MWBS Memory Write Burst Size (in D-words) MRBS Memory Read Burst Size (in D-words) MWDR Memory Write Data Register MWDX Memory Write Data Reg. - Byte Swapping MRDR Memory Read Data Register MRDX Memory Read Data Reg. - Byte Swapping FCB Buffer & Stack Management FCBBA Frame Control Buffer - Base Address FCBAG Frame Control Buffer - Buffer Aging Status FCBSL FCBST FCBSS Frame Ctrl Buffer Stack - Size Limit Frame Ctrl Buffer Stack - Buffer Low Threshold Frame Ctrl Buffer Stack - Allocation Status
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
I/O Offset Little Big Endian Endian hC00 hC10 hC20 hC30 hC40 hC40 hC70 hC80 hC90 hCA0 hCB0 hCC0 hCD0 hCE0 hC02 hC12 hC22 hC32 hC40 hC40 hC72 hC82 hC92 hCA2 hCB2 hCC2 hCD2 hCE2 hn02 hn12 hn22 hn32 hn42 hn52 hn68 hn78 Reg. Size 16-bit 16-bit 16-bit 16-bit 32-bit 32-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit 32-bit W/R Note:
Register
Description
Access Control Function (Chip Level controls) AVXR VLAN Control Table (VCT) Index Register AVDR VCT Data Register AVTC VLAN Type Code AXSC Transmission Scheduling Control Register AMIIC MII Command Register AMIIS MII Status Register AFCR Flow Control Register AMAR0 Multicast Address. for MAC Control Frames AMAR1 Byte [3,2] AMAR2 Byte [5,4] AMCT MAC Control FrameType Code Register ADAR0 Base MAC Address Register - Byte [1,0] ADAR1 Base MAC Address Register - Byte [3,2] ADAR2 Base MAC Address Register - Byte [5,4]
Byte [1,0]
W/-W/R W/R W/R W/---/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R W/R --/R --/R --/R --/R --/R
Ethernet MAC Port Control Registers - (substitute [n] with Port Number, n = {0..3] ) ECR0 MAC Port Control Register hn00 ECR1 MAC Port Configuration Register hn10 ECR2 MAC Port Interrupt Mask Register hn20 ECR3 MAC Port Interrupt Status Register hn30 EXSR MAC Tx Status Register hn40 EXEC ERSR EREC MAC Tx Error Counters MAC Rx Status Register MAC Rx Error Counters hn50 hn68 hn78
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.3 XpressFlow Bus Operation
Zarlink's optimized XpressFlow Bus architecture Provides 1.6G bps switching bandwidth -33 -40 -50 1.07G bps 1.28G bps 1.6G bps
EA218E 8-Port 10Mb Ethernet Access Controller
Command Messages for passing control information between devices Data Messages for forwarding an Ethernet frame from receiving port to transmission port Built-in intelligent bus load regulator for data traffic balancing Provides centralized bus arbitration with two level request priorities High priority for Data Messages Low priority for Command Messages
Full multi bus master structure Allows XpressFlow Engine to communicate with Access Controllers via a message passing protocol
2.3.1 Pin Description
Symbol S_D[31:0] Type CMOS I/O-TS Name and Functions
S_MSGEN#
S_EOF#
S_IRDY
S_TABT# S_HPREQ# S_REQ# S_GNT# S_OVLD# S_CLK
Data Bus Bit [31:0] - a 32-bit synchronous data bus. Note: During the system RESET period, Data Bit [31:28] are used as Processor Interface Configuration bit [0:3] CMOS Message Envelope - encompasses the entire period of a message transfer. Targets use the I/O-TS leading edge of this signal to detect the beginning of a message transfer, and to decode the message header for the intended target(s). CMOS End of Frame - only used by frame data transfer messages to identify the end of frame condiI/O-TS tion. This signal is synchronous with the Rx Frame Status word appended to the end of the message. CMOS Initiator Ready - a normal true signal. When negated, it indicates the initiator had asserted wait I/O-TS state(s) in between command words. Target should use this signal as enable signal for latching the data from the bus. CMOS Target Abort - when asserted, the target had aborted the reception of current message on the I/O-OD bus. CMOS High Priority Request - indicates one or more Bus Requester is requesting for high priority I/O-OD message transfer. CMOS Bus Request -Bus Request signals from Access Controller to Bus Access Arbitrator in XpressOutput Flow Engine CMOS In- Bus Grant -Bus Grant signals from Bus Arbitrator to Bus Requester put CMOS Bus Overload - when asserted, all data forwarding bus bandwidth has been allocated. Cannot Output support additional load for data forwarding traffic. CMOS XpressFlow Bus Clock - 33MHz system clock Input
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.3.2 Bus Cycle Waveforms
S_CLK
EA218E 8-Port 10Mb Ethernet Access Controller
S_MSGEN#
S_D[31:0]
C0
C1
D0
D1
D2
D3
D4
D5
EoF
S_EOF#
S_IRDY
XpressFlow Bus Data Transfer Cycle
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
C0
C1
EOF
C0
C1
S_EOF#
S_TABT#
Command Cycle
Data Xfer w/o Data
Aborted Command
Other XpressFlow Bus Cycles
S_CLK
S_REQ[k]#
S_REQ[j]# S_HPREQ#
High Priority Request pre-empts the low priority request.
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
S_CLK
S_MSGEN#
S_REQ[j]#
S_GNT[j]#
S_HPREQ#
S_REQ[I]#
S_GNT[I]#
XpressFlow Bus arbitration
S_CLK
S_REQ[k]#
S_OVLD#
Bus Overload pre-empts the data transfer request
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset 2.4 10Mb Serial Interface for Port 0 through 7
Fully compliant with IEEE 802.3 10M bit Serial Interface Standard for connecting with external 10Mbps Ethernet Physical Layer Transceiver
EA218E 8-Port 10Mb Ethernet Access Controller
Supports 10Mbps 10BaseT serial interface Supports both half and full duplex operation
2.4.1 Pin Description
Symbol Tn_RXD Tn_RXC Tn_TXC Tn_TXEN Tn_TXD Tn_LPBK Tn_FD Tn_COL Tn_CRS Tn_LNK Note: Type TTL In (5VT) TTL In (5VT) TTL In (5VT) CMOS Output CMOS Output CMOS Output CMOS Output TTL In (5VT) TTL In (5VT) TTL In (5VT) Name and Functions Receive Data - (one for each 10M bit Serial Interface Port) a receive data stream. Receive Clock - (one for each 10M bit Serial Interface Port) from external phy for sampling the receive data from Tn_RXD input Transmit Clock - (one for each 10M bit Serial Interface Port) a continuous clock input with 35% to 65% duty cycles. Transmit Enable - (one for each 10M bit Serial Interface Port) Transmit Data - (one for each 10M bit Serial Interface Port) a transmit data stream. Loop Back Enable - (one for each 10M bit Serial Interface Port) The polarity of this signal is programmable via Port Configuration Register Full Duplex Mode - (one for each 10M bit Serial Interface Port) The polarity of this signal is programmable via Port Configuration Register Collision Detected - (one for each 10M bit Serial Interface Port) Carrier Sense - (one for each 10M bit Serial Interface Port) Link Status - (one for each 10M bit Serial Interface Port) The polarity of this signal is programmable via Port Configuration Register
"n" is the port number [7:0] These signals have programmable output polarity.
100 nsec TXC
TXEN
TXD
10M bit Serial Interface - Transmit Timing
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
CRS 100 nsec RXC
RXD
10M bit Serial Interface - Receive Timing
2.5 Test Pins
Symbol T_MODE Type CMOS I/O-TS Name and Functions Test Mode Selection & Test Output - Set Test Mode upon Reset, and provides test status output during test mode
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
3. DC SPECIFICATION
3.1 ABSOLUTE MAXIMUM RATINGS
Storage Temperature Operating Temperature Supply Voltage VDD with Respect to VSS Voltage on 5V Tolerant Input Pins Voltage on Other Input Pins -50C to +125C 0C to +70C +3.0 V to +3.6 V -0.5 V to (VDD + 1.8 V) -0.5 V to (VDD + 10%)
Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
3.2 DC CHARACTERISTICS
VDD = +3.0 V to +3.6 V TAMBIENT = 0C to +70C Preliminary Symbol fosc Parameter Description Frequency of Operation (-40) Frequency of Operation (-50) Frequency of Operation (-66) Supply Power - @ 40 MHz (VDD =3.3 V) Supply Power - @ 50 MHz (VDD =3.3 V) Supply Power - @ 66.67 MHz (VDD =3.3 V) Output High Voltage (CMOS) IOH = maximum Output Low Voltage (CMOS) IOL = maximum Output High Voltage (TTL) IOH = maximum Output Low Voltage (TTL) IOL = maximum Input High Voltage (CMOS) Input Low Voltage (CMOS) Input High Voltage (TTL) Input Low Voltage (TTL) Input High Voltage (TTL 5V tolerant) Input Low Voltage (TTL 5V tolerant) Input Leakage Current (0.1 V VIN VDD) (all pins except those with internal pull-up/pull-down resistors) Output Leakage Current (0.1 V VOUT VDD) Input Leakage Current VIH = VDD - 0.1 V (pins with internal pull-down resistors) Input Leakage Current VIL = 0.1 V (pins with internal pull-up resistors) Input Capacitance Output Capacitance I/O Capacitance Min 20 20 20 300 300 360 VDD - 0.5 0.45 2.4 VDD x 70% -0.5 2.0 -0.3 2.0 -0.3 0.45 VDD + 10% VDD x 30% VDD + 10% +0.8 VDD + 1.8 +0.8 10 Type Max 40.0000 50.0000 66.6667 500 500 600 Unit MHz MHz MHz mA mA mA V V V V V V V V V V A
IDD
VOH-CMOS VOL-CMOS VOH-TTL VOL-TTL VIH-CMOS VIL-CMOS VIH-TTL VIL-TTL VIH-5VT VIL-5VT ILI
ILO IIH IIL CIN COUT CI/O Notes:
15 60 -60 8 8 10
A A A pF pF pF
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
4. AC SPECIFICATION
4.1 XpressFlow Bus Interface:
S_CLK
S_D[31:0] S17 S18 S13 S2-min S_MSGEN# S19 S20 S14 S3-min S_EOF# S21 S22 S15 S4-min S_IRDY S23 S24 S_CLK S12 S1-min
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S27 S28
XpressFlow Bus Interface - Output float delay timing
S_TABT#
S29 S30 S_CLK S1-max S1-min S_D[31:0] S32 S2-max S2-min S_MSGEN# S34 S3-max S3-min S_EOF#
S_HPREQ#
S31
S_GNT#
S33
S_OVLD# XpressFlow Bus Interface - Input setup and hold timing
S_IRDY
S4-max S4-min
S6-max S6-min S_TABT# S7-max S7-min S_HPREQ# S8-max S8-min S_REQ#
XpressFlow Bus Interface -
Output valid delay timing
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset
-40 Symbol S1 S2 S3 S4 S6 S7 S8 S12 S13 S14 S15 S17 S18 S19 S20 S21 S22 S23 S24 S27 S28 S29 S30 S31 S32 S33 S34 Parameter S_D[31:0] output valid delay S_MSGEN# output valid delay S_EOF# output valid delay S_IRDY output valid delay S_TABT# output valid delay S_HPREQ# output valid delay S_REQ# output valid delay S_D[31:0] output float delay S_MSGEN# output float delay S_EOF# output float delay S_IRDY output float delay S_D[31:0] input set-up time S_D[31:0] input hold time S_MSGEN# input set-up time S_MSGEN# input hold time S_EOF# input set-up time S_EOF# input hold time S_IRDY input set-up time S_IRDY input hold time S_TABT# input set-up time S_TABT# input hold time S_HPREQ# input set-up time S_HPREQ# input hold time S_GNT# input set-up time S_GNT# input hold time S_OVLD# input set-up time S_OVLD# input hold time 2 5.5 2 5.5 2 5.5 2 5.5 13 5.5 2 5.5 13 5.5 15 5.5 Min (ns) 6 6 6 6 6 6 6
EA218E 8-Port 10Mb Ethernet Access Controller
-50 Max (ns) 14 14 14 14 14 14 14 18 18 18 18 1.5 4.5 1.5 4.5 1.5 4.5 1.5 4.5 10 4.5 1.5 4.5 10 4.5 12 4.5 Min (ns) 5 5 5 5 5 5 5 Max (ns) 11 11 11 11 11 11 11 15 15 15 15 1 3.5 1 3.5 1 3.5 1 3.5 8 3.5 1 3.5 8 3.5 9 3.5 Min (ns) 4 4 4 4 4 4 4 -66 Max (ns) 8.5 8.5 8.5 8.5 8.5 8.5 8.5 12 12 12 12 CL = 50pf CL = 50pf CL = 50pf CL = 50pf CL = 50pf CL = 50pf CL = 20pf Note:
AC Characteristics - XpressFlow Bus Interface
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset 4.2 CPU Bus Interface:
P_CLK
P15 P16-min
EA218E 8-Port 10Mb Ethernet Access Controller
P_CLK
P1 P2
P_RST#
P3 P4
P_D[31:0]
CPU Bus Interface - Output float delay timing
P_ADS#
P5 P6
P_CLK
P16-max P16-min
P_W/R#
P7 P8
P_D[15:0]
P17-max P17-min
P_CS#
P9 P10
P_RDY#
P18-max P18-min
P_A[11:1]
P11 P12
P_INT CPU Bus Interface -
P_D[15:0] CPU Bus Interface - Input setup and hold timing
Output valid delay timing
-40 Symbol P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P15 P16 P17 P18 Parameter P_RST# input setup time P_RST# input hold time P_ADS# input set-up time P_ADS# input hold time P_W/R# input set-up time P_W/R# input hold time P_CS# input set-up time P_CS# input hold time P_A[11:1] input set-up time P_A[11:1] input hold time P_D[31:0]# input set-up time P_D[31:0]# input hold time P_D[31:0]# output float delay P_D[31:0]# # output valid delay P_RDY# output valid delay P_INT# output valid delay Min (ns) 13 3.5 13 3.5 13 3.5 13 3.5 13 3.5 13 3.5 17 8.5 8.5 17 Max (ns) Min (ns) 10 2.5 10 2.5 10 2.5 10 2.5 10 2.5 10 2.5 13 6.5 6.5 13 -50 Max (ns)
-66 Min (ns) 8 2 8 2 8 2 8 2 8 2 8 2 10 5 5 10 CL = 60pf CL = 60pf CL = 20pf Max (ns) Note:
AC Characteristics -- CPU Bus Interface
(c) 1998 Zarlink Semiconductor, Inc.
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XpressFlow-2020 Series - Ethernet Switch Chipset 4.3 Local Memory Interface:
L_CLK
L1 L2
EA218E 8-Port 10Mb Ethernet Access Controller
L_CLK
L3-max L3-min
L_D[31:0] Local Memory Interface - Input setup and hold timing
L_D[31:0]
L4-max L4-min
L_A[19:2]
L5-max L5-min
L_CLK
L10 L3-min
L_CS[3:0]#
L6-max L6-min
L_D[31:0]
L_ADSC#
L7-max L7-min
Local Memory Interface - Output float delay timing
L_BWE[3:0]#
L8-max L8-min
L_WE#]
L9-max L9-min
L_OE# Local Memory Interface - Output valid delay timing
-40 Symbol L1 L2 L3 L4 L6 L7 L8 L9 L10 Parameter L_D[31:0]# input set-up time L_D[31:0]# input hold time L_D[31:0]# output valid delay L_A[19:2] output valid delay L_ADSC# output valid delay L_BWE[3:0]# output valid delay L_WE# output valid delay L_OE# output valid delay L_D[31:0]# output float delay Min (ns) 6.5 3 17 17 17 17 17 17 22 Max (ns) Min (ns) 5.5 2.5
-50 Max (ns) Min (ns) 4 2 13 13 13 13 13 13 18
-66 Max (ns) Note:
10 10 10 10 10 10 14
CL = 30pf CL = 30pf CL = 30pf CL = 30pf CL = 10pf CL = 10pf
AC Characteristics - Local Memory Interface
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XpressFlow-2020 Series - Ethernet Switch Chipset
EA218E 8-Port 10Mb Ethernet Access Controller
5. PACKAGING INFORMATION
352-PIN BGA (35x35x2.33mm)
Pin 1 I.D. B
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 0.75 DIA +/- 0.15 (352X)
A
24.00 Ref 32.00 Ref 1.17 Ref 35.00 +/- 0.20
1.27 31.75
C 0.56 2.33 Ref +/-0.13 0.60 +/-0.10
Ordering Information Part Number EA218E Description 8-port 10Mbps Ethernet network access Environmental - C = Commercial I = Industrial 0 = 40 MHz 5 = 50 MHz 6 = 66 MHz B = BGA Identification C0B Zarlink Use TAV Revision 001 = Rev.1 For latest revision, leave blank Revision rrr
Speed grade -
Package -
This Document contains preliminary information on a product. Zarlink Semiconductor Inc. reserves the right to make any changes without notice.
400 March Road Ottawa, Ontario, Canada K2K 3H4 Tel. 613 592 0200, FAX: 613 592 1010 Web Site: www.zarlink.com
Rev. 2.1 February 1999
1998 Zarlink Semiconductor Inc.
E1
E
DIMENSION A A1 A2 D D1 E E1 b e
MIN MAX 2.20 2.46 0.50 0.70 1.17 REF 35.20 34.80 30.00 REF 35.20 34.80 30.00 REF 0.60 0.90 1.27 352 Conforms to JEDEC MS - 034
e
D1 D
A2
A1
A
1. CONTROLLING DIMENSIONS ARE IN MM 2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 4. N IS THE NUMBER OF SOLDER BALLS 5. NOT TO SCALE. 6. SUBSTRATE THICKNESS IS 0.56 MM
c Zarlink Semiconductor 2002 All rights reserved.
Package Code Previous package codes:
ISSUE ACN DATE APPRD.
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